Single crystal wafers, of which typical examples are those of silicon (Si) and gallium arsenide (GaAs), are obtained by slicing a single crystal ingot produced by the Czochralski method (CZ method) or the floating zone method (FZ method) into wafers. Therefore, it is desired to obtain wafers as many as possible from one ingot by making thickness of wafer as small as possible or reducing the stock removal for slicing. That is, desirability of reducing thickness of wafers or processing loss in the production of wafers to reduce waste of the raw material and thereby reduce production cost of wafers has hitherto been widely recognized.
However, if thickness of wafer is simply reduced, it becomes likely that breakage or chipping occurs in the wafer production process or device production process. Therefore, it is considered that wafers must have a certain thickness (for example, about 700 to 800 μm in the case of a silicon wafer having a diameter of 200 mm). Further, since a limitation is imposed on the reduction of stock removal for slicing by slicing apparatus, the reduction of stock removal for slicing suffers from a certain limit.
Furthermore, loss of the raw material is generated not only in the wafer production process, but also in the device production process. Since the final thickness of wafer actually mounted as a chip is about 100 to 200 μm, a step of reducing the thickness from the back surface (back lap) is used, and thus the raw material is wasted also in this step.
Meanwhile, a gate insulator film of MIS (metal/insulator film/silicon) type transistor mainly produced by using a silicon single crystal wafer is required to have highly efficient electric characteristics and high reliability such as low leakage current characteristic, low interface state density and high carrier injection resistance. As a technique for forming a gate insulator film satisfying these requirements, there has conventionally been utilized the thermal oxidation technique using oxygen molecules or water molecules at 800° C. or higher. Conventionally, in order to obtain good oxide film/silicon interface characteristics, oxide dielectric breakdown voltage characteristic and leakage current characteristic by using the thermal oxidation technique, there must be used a silicon wafer having a {100} plane for the surface or a silicon wafer having a plane orientation tilting by about 4° from a {100} plane of a single crystal.
If a gate oxide film is formed on a silicon wafer having a plane orientation other than those mentioned above by using the thermal oxidation technique, electric characteristics are degraded, that is, the interface state density of oxide film/silicon interface becomes high, the oxide dielectric breakdown voltage characteristic and leakage current characteristic are degraded and so forth. Therefore, as a silicon wafer on which semiconductor devices such as MIS type transistors are formed, a silicon wafer having a {100} plane for the surface or a silicon wafer having a plane orientation tilting by about 4° from a {100} plane of a single crystal has conventionally been used.
However, in a silicon wafer having a {100} plane for the surface, a {110} plane serving as a cleavage plane exists perpendicularly to the surface. Thus, breakages, chipping, slip dislocations and so forth are likely to be caused during the process. Therefore, a usually used silicon wafer having a {100} plane for the surface has a thickness of about 700 to 800 μm for a diameter of 200 mm or a thickness of about 600 to 700 μm for a diameter of 150 mm, and the same shall apply to a silicon wafer having a plane orientation tilting by about 4° from a {100} plane of a single crystal.
Recently, a technique was developed for forming an insulator film of good quality irrespective of the plane orientation of silicon wafer surface (refer to 2000 Symposium ON VLSI Technology, Honolulu, Hi., Jun. 13-15, 2000 “Advantage of Radical Oxidation for Improving Reliability of Ultra-Thin Gate Oxide”). Therefore, it can be said that, thanks to such a technique, it became unnecessary to limit the plane orientation of wafer for the production of MIS type semiconductor devices to the {100} surface.